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| EMC646SP16J Datasheet, PDF (58/65 Pages) Emerging Memory & Logic Solutions Inc – 4Mx16 bit CellularRAM | |||
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Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 47. Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
VIH
CLK
VIL
A[21:0] VIH
VIL
VIH
ADV#
VIL
CE# VIH
VIL
OE# VIH
VIL
VIH
WE#
VIL
VIH
LB#/UB#
VIL
VOH
WAIT
High-Z
VOL
VOH
DQ[15:0]
High-Z
VOL
tSP
tHD
Valid Address
tSP tHD
tCSP
tSP tHD
tSP
tCEW
tCLK
tWC
Valid Address
tAW
tWR
tBOE
tOLZ
tHD
tCBPH
tHZ Note 2
tOHZ
tCW
tAS
tWP
tWPH
tKHTL
tACLK
tKOH
Valid Output
tCEW
High-Z
VIH
VIL
tBW
tHZ
tDW tDH
Valid Input
READ Burst Identified
(WE# = HIGH)
Donât Care
Note:
1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: Fixed or variable latency; latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from
fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM.
A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
Undefined
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