EMC646SP16J Datasheet, PDF (18/65 Pages) Emerging Memory & Logic Solutions Inc – 4Mx16 bit CellularRAM

Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 11: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
CLK
A[21:0]
(except A[19:18])
A[19:18]²
CRE
Latch control register value
OPCODE
t_HD
t_SP
t_SP
t_HD
ADV#
t_{SP tHD}
CE#
t_CSP
Latch control register address
Address
Address
t_CBPH3
OE#
WE#
t_SP
t_HD
LB#/UB#
WAIT
t_CEW
High-Z
High-Z
DQ[15:0]
Note:
1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
collisions require a corresponding number of additional CE# LOW cycles.
Data
Valid
Don’t Care
18