EPVP6800 Datasheet, PDF (29/47 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6800
VFD Controller
Bit 3 (CNT3S) : COUNTER3 clock source
0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
1 system clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
Bit 4 ~ Bit 6 (C4_PSC0 ~ C4_PSC2) : COUNTER4 prescaler ratio
C4_PSC2 C4_PSC1 C4_PSC0 COUNTER4
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 7 (CNT4S) : COUNTER4 clock source
0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
1 system clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
7.3.6 IOCA
a) PAGE 1 (Clock Source and Prescaler for COUNTER5 )
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
Bit 1
Bit 0
CNT5S C5_PSC2 C5_PSC1 C5_PSC0
-
-
-
-
R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 2 (C5_PSC0 ~ C5_PSC2) : COUNTER5 prescaler ratio
C5_PSC2 C5_PSC1 C5_PSC0 COUNTER4
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 3 (CNT5S) : COUNTER5 clock source
0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
1 system clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
This specification is subject to change without further notice.
11.28.2004 (V123) 23 of 47