EPVP6800 Datasheet, PDF (19/47 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6800
VFD Controller
7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer),
ADC Output Data Buffer , Counter3 Data
a) PAGE 0 (PLL Enable Bit, Main Clock Selection Bits,
Watchdog Timer Enable Bit)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IDLE PLLEN CLK2
CLK1
CLK0
-
-
R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
Bit 0
WDTEN
R/W-0
Bit 0 (WDTEN) : Watch dog control bit
You can use WDTC instruction to clear watch dog counter. The counter clock
source is 32768/2 Hz. If the prescaler is assigned to TCC, Watch dog will time out
by (1/32768 )*2 * 256 = 15.616mS. If the prescaler is assigned to WDT, the time out
interval will be longer depending on the prescaler. Ratio.
0/1 disable/enable
Bit 1~Bit 2 : Unused
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
You can select different frequencies for the main clock with CLK1 and CLK2. All the
available clock selections are listed below.
PLLEN CLK2 CLK1 CLK0 Sub clock MAIN clock
CPU clock
1
0
0
0
32.768kHz 447.829kHz 447.829kHz (Normal mode)
1
0
0
1
32.768kHz 895.658kHz 895.658kHz (Normal mode)
1
0
1
0
32.768kHz 1.791MHz 1.791MHz (Normal mode)
1
0
1
1
32.768kHz 3.582MHz 3.582MHz (Normal mode)
1
1
0
0
32.768kHz 7.165MHz 7.165MHz (Normal mode)
1
1
0
1
32.768kHz 10.747MHz 10.747MHz (Normal mode)
1
1
1
0
32.768kHz 14.331MHz 14.331MHz (Normal mode)
1
1
1
1
32.768kHz 17.91MHz 17.91MHz (Normal mode)
0 Don’t care Don’t care Don’t care 32.768kHz Don’t care 32.768kHz (Green mode)
Bit 6 (PLLEN) :
PLL's power control bit which is CPU mode control register
0/1 disable PLL/enable PLL
If PLL is enabled, CPU will operate at normal mode (high frequency). Otherwise, it
will run at green mode (low frequency, 32768 Hz).
447.8293kHz ~17.9132MHz
PLL circuit
CLK2 ~ CLK0
ENPLL
1
switch
0
System clock
Sub-clock
32.768kHz
Fig. 4 The Relation Between 32.768kHz and PLL
This specification is subject to change without further notice.
11.28.2004 (V123) 13 of 47