EPVP6810 Datasheet, PDF (23/50 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6810
VFD Controller
Bit 7 (IDLE) : SLEEP or IDLE mode control as set by SLEP instruction.
0/1 SLEEP mode/IDLE mode.
This bit allows SLEP instruction to decide which power saving mode to
execute. The status after wake-up and the wake-up source list is as the shown
below.
Wakeup Signal
SLEEP Mode
IDLE Mode
RA(7,6)=(0,0)
+ SLEP
RA(7,6)=(1,0)
+ SLEP
TCC time out
IOCF Bit0=1
No function
1) Wake-up
2) Jump to next instruction after SLEP
COUNTER1 time out
IOCF Bit1=1
No function
1) Wake-up
2) Jump to next instruction after SLEP
COUNTER2 time out
IOCF Bit2=1
No function
1) Wake-up
2) Jump to next instruction after SLEP
COUNTER3 time out
IOCD Bit0=1
No function
1) Wake-up
2) Jump to next instruction after SLEP
COUNTER4 time out
IOCD Bit1=1
No function
1) Wake-up
2) Jump to next instruction after SLEP
COUNTER5 time out
IOCD Bit2=1
No function
1) Wake-up
2) Jump to next instruction after SLEP
PORT90(IR function)
IOCF Bit3=1
Reset and jump 1) Wake-up
to Address 0 2) Jump to next instruction after SLEP
WDT time out
Reset and jump 1) Wake-up
to Address 0 2) Next instruction
PORTC(0~3)(Key1~Key4)
Reset and Jump 1) Wake-up
RE PAGE0 Bit3 or Bit4 or Bit5 or Bit6 = 1 to Address 0 2) Jump to next instruction after SLEP
PORT9(1~4)
IOCF Bit4 or Bit5 or Bit6 =1 or Bit7=1
Reset and Jump 1) Wake-up
to Address 0 2) Jump to next instruction after SLEP
NOTES: 1 PORT90 wakeup function is controlled by IOCF Bit 3. It is a falling edge or rising edge
trigger (controlled by CONT register Bit7).
2. PORT91 wakeup function is controlled by IOCF Bit 4. It is a falling edge trigger.
3. PORT92 ~ PORT94 wakeup functions are controlled by IOCF. They are falling edge
triggers.
4. PORTC0 ~ PORTC3 wakeup functions are controlled by RE PAGE0 Bit 0 ~ Bit 3. They are
falling edge triggers.
b) PAGE 1 (ADC Output Data Register)
Bit 7
AD7
Bit 6
AD6
Bit 5
AD5
Bit 4
AD4
Bit 3
AD3
R
R
R
R
R
Bit 2
AD2
R
Bit 1
AD1
R
Bit 0 ~ Bit 7 (AD01~ AD7) : These 8 bits are full ADC data buffer
Bit 0
AD0
R
This specification is subject to change without further notice.
11.28.2004 (V1.23)17 of 50