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HB54R1G9F2U Datasheet, PDF (9/16 Pages) Elpida Memory – 1GB Registered DDR SDRAM DIMM | |||
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HB54R1G9F2U-A75B/B75B/10B
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
PLL
OUT1
SDRAM
stack
120â¦
CK0
/CK0
120â¦
IN
120â¦
OUT'N'
C
Feedback
SDRAM
stack
240⦠Register1
(Typically two registers per DIMM)
240⦠Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0 ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Data Sheet E0192H30 (Ver. 3.0)
9
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