HB54R1G9F2U Datasheet, PDF (5/16 Pages) Elpida Memory – 1GB Registered DDR SDRAM DIMM

HB54R1G9F2U-A75B/B75B/10B
Serial PD Matrix*¹
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08
Memory type
0 0 0 0 0 1 1 1 07
Number of row address
0 0 0 0 1 1 0 1 0D
Number of column address
0 0 0 0 1 0 1 1 0B
Number of DIMM banks
0 0 0 0 0 0 1 0 02
Module data width
0 1 0 0 1 0 0 0 48
Module data width continuation
0 0 0 0 0 0 0 0 00
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04
DDR SDRAM cycle time, CL = X
-A75B
0 1 1 1 0 0 0 0 70
-B75B
0 1 1 1 0 1 0 1 75
-10B
SDRAM access from clock (tAC)
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
0 1 1 1 0 1 0 1 75
1 0 0 0 0 0 0 0 80
DIMM configuration type
0 0 0 0 0 0 1 0 02
12
Refresh rate/type
1 0 0 0 0 0 1 0 82
13
Primary SDRAM width
0 0 0 0 0 1 0 0 04
14
Error checking SDRAM width
0 0 0 0 0 1 0 0 04
SDRAM device attributes:
15
Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0E
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
18
SDRAM device attributes:
/CAS latency
19
SDRAM device attributes:
/CS latency
0 0 0 0 1 1 0 0 0C
0 0 0 0 0 0 0 1 01
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02
21
SDRAM module attributes
0 0 1 0 0 1 1 0 26
22
SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0
Minimum clock cycle time at
23
CLX - 0.5
-A75B
0 1 1 1 0 1 0 1 75
-B75B/10B
1 0 1 0 0 0 0 0 A0
Maximum data access time (tAC) from
24
clock at CLX - 0.5
0 1 1 1 0 1 0 1 75
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
Comments
128
256 byte
SDRAM DDR
13
11
2
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*⁵
0.75ns*⁵
0.8ns*⁵
ECC
7.8 µs
Self refresh
×4
×4
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*⁵
0.75ns*⁵
0.8ns*⁵
20ns
Data Sheet E0192H30 (Ver. 3.0)
5