HB52F328DC-75B Datasheet, PDF (7/22 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 133 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC133 SDRAM

HB52F328DC-75B/75BL
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0 0 0 0 0 0 0 1 01
0
W latency
21
SDRAM module attributes
0 0 0 0 0 0 0 0 00
Non buffer
22
SDRAM device attributes:
0 0 0 0 1 1 1 0 0E
General
V_CC ± 10%
23
SDRAM cycle time
1 0 1 0 0 0 0 0 A0
(2nd highest CE latency)
10 ns
CL = 2
24
SDRAM access from Clock 0 1 1 0 0 0 0 0 60
(2nd highest CE latency)
6 ns
25
SDRAM cycle time
0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
26
SDRAM access from Clock 0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
27
Minimum row precharge time 0 0 0 1 0 1 0 0 14
20 ns
28
Row active to row active min 0 0 0 0 1 1 1 1 0F
15 ns
29
RE to CE delay min
0 0 0 1 0 1 0 0 14
20 ns
30
Minimum RE pulse width
0 0 1 0 1 1 0 1 2D
45 ns
31
Density of each bank on
0 0 1 0 0 0 0 0 20
module
2 bank
128M byte
32
Address and command signal 0 0 0 1 0 1 0 1 15
input setup time
1.5 ns
33
Address and command signal 0 0 0 0 1 0 0 0 08
input hold time
0.8 ns
34
Data signal input setup time 0 0 0 1 0 1 0 1 15
1.5 ns
35
Data signal input hold time 0 0 0 0 1 0 0 0 08
0.8 ns
36 to 61 Superset information
0 0 0 0 0 0 0 0 00
Future use
62
SPD data revision code
0 0 0 1 0 0 1 0 12
Rev. 1.2B
63
Checksum for bytes 0 to 62 0 0 1 1 1 0 1 0 3A
58
64
Manufacturer’s JEDEC ID code 0 0 0 0 0 1 1 1 07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00
72
Manufacturing location
× × × × × × × × ××
*² (ASCII-
8bit code)
Data Sheet E0085H10
7