HB52F328DC-75B Datasheet, PDF (15/22 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 133 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC133 SDRAM

HB52F328DC-75B/75BL
DC Characteristics (Ta = 0 to 65°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52F328DC-75B/75BL
PC133
PC100
CE latency = 3 CE latency = 2
Parameter
Symbol Min Max Min Max Unit Test conditions
Notes
Operating current
I _CC1
—
Standby current in power I_CC2P
—
down
580 —
24
—
520 mA Burst length = 1
t_RC = min
1, 2, 3
24
mA CKE = V_IL, t_CK = 12 ns 6
Standby current in power I_CC2PS —
down (input signal stable)
Standby current in non I_CC2N
—
power down
Active standby current in I_CC3P
—
power down
16
—
160 —
32
—
16
mA CKE = V_IL, CK0/CK1 = 7
V_IL or V_IH Fixed
160
mA CKE, S = V_IH,
4
t_CK = 12 ns
32
mA CKE = V_IH, t_CK = 12 ns 1, 2, 6
Active standby current in I_CC3N
—
non power down
Burst operating current I_CC4
—
Refresh current
I _CC5
—
Self refresh current
I _CC6
—
Self refresh current
(L-version)
I _CC6
—
240 —
700 —
1000 —
24
—
16
—
240
560
1000
24
16
mA CKE, S = V_IH,
t_CK = 12 ns
mA t_CK = min, BL = 4
mA t_RC = min
mA V_IH ≥ V_CC – 0.2 V
V_IL ≤ 0.2 V
mA
1, 2, 4
1, 2, 5
3
8
Input leakage current
I _LI
Output leakage current I_LO
–10 10
–10 10
–10 10
–10 10
µA 0 ≤ Vin ≤ V_CC
µA 0 ≤ Vout ≤ V_CC
DQ = disable
Output high voltage
V_OH
2.4
—
2.4
—
V I_OH = –4 mA
Output low voltage
V_OL
—
0.4
—
0.4
V I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
Data Sheet E0085H10
15