HB52F328DC-75B Datasheet, PDF (17/22 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 133 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC133 SDRAM

HB52F328DC-75B/75BL
AC Characteristics (Ta = 0 to 65°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52F328DC-75B/75BL
PC133
PC100
CE latency = 3 CE latency = 2
Parameter
PC100
Symbol Symbol Min
Max Min
Max Unit Notes
System clock cycle time
t _CK
Tclk 7.5
—
10
—
ns 1
CK high pulse width
t _CKH
Tch 2.5
—
3
—
ns 1
CK low pulse width
t _CKL
Tcl
2.5
—
3
—
ns 1
Access time from CK
t _AC
Tac —
5.4
—
6
ns 1, 2
Data-out hold time
t _OH
Toh 2.7
—
3
—
ns 1, 2
CK to Data-out low impedance
t _LZ
2
—
2
—
ns 1, 2, 3
CK to Data-out high impedance
t _HZ
—
5.4
—
6
ns 1, 4
Data-in setup time
t _DS
Tsi
1.5
—
2
—
ns 1
Data in hold time
t _DH
Thi
0.8
—
1
—
ns 1
Address setup time
t _AS
Tsi
1.5
—
2
—
ns 1
Address hold time
t _AH
Thi
0.8
—
1
—
ns 1
CKE setup time
t _CES
Tsi
1.5
—
2
—
ns 1, 5
CKE setup time for power down exit t_CESP
Tpde 1.5
—
2
—
ns 1
CKE hold time
t _CEH
Thi
0.8
—
1
—
ns 1
Command setup time
t _CS
Tsi
1.5
—
2
—
ns 1
Command hold time
t _CH
Thi
0.8
—
1
—
ns 1
Ref/Active to Ref/Active command t_RC
Trc
67.5
—
70
—
ns 1
period
Active to precharge command
period
t _RAS
Tras 45
120000 50
120000 ns 1
Active command to column
command (same bank)
t _RCD
Trcd 20
—
20
—
ns 1
Precharge to active command
t _RP
Trp
20
—
20
—
ns 1
period
Write recovery or data-in to
precharge lead time
t _DPL
Tdpl 15
—
20
—
ns 1
Active (a) to Active (b) command t_RRD
Trrd 15
—
20
—
ns 1
period
Transition time (rise and fall)
t_T
Refresh period
t _REF
1
5
1
5
ns
—
64
—
64
ms
Data Sheet E0085H10
17