HB52F328DC-75B Datasheet, PDF (6/22 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 133 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC133 SDRAM

HB52F328DC-75B/75BL
Serial PD Matrix*¹
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
1 0 0 0 0 0 0 0 80
128
module manufacturer
1
Total SPD memory size
0 0 0 0 1 0 0 0 08
256 byte
2
Memory type
0 0 0 0 0 1 0 0 04
SDRAM
3
Number of row addresses bits 0 0 0 0 1 1 0 1 0D
13
4
Number of column addresses 0 0 0 0 1 0 0 1 09
9
bits
5
Number of banks
0 0 0 0 0 0 1 0 02
2
6
Module data width
0 1 0 0 0 0 0 0 40
64
7
Module data width (continued) 0 0 0 0 0 0 0 0 00
0 (+)
8
Module interface signal levels 0 0 0 0 0 0 0 1 01
LVTTL
9
SDRAM cycle time
(highest CE latency)
7.5 ns
0 1 1 1 0 1 0 1 75
CL = 3
10
SDRAM access from Clock 0 1 0 1 0 1 0 0 54
(highest CE latency)
5.4 ns
11
Module configuration type
0 0 0 0 0 0 0 0 00
Non parity
12
Refresh rate/type
1 0 0 0 0 0 1 0 82
Normal
(7.8125 µs)
Self refresh
13
SDRAM width
0 0 0 1 0 0 0 0 10
16M × 16
14
Error checking SDRAM width 0 0 0 0 0 0 0 0 00
—
15
SDRAM device attributes:
0 0 0 0 0 0 0 1 01
minimum clock delay for back-
to-back random column
addresses
1 CLK
16
SDRAM device attributes:
0 0 0 0 1 1 1 1 0F
Burst lengths supported
1, 2, 4, 8
17
SDRAM device attributes:
0 0 0 0 0 1 0 0 04
4
number of banks on SDRAM
device
18
SDRAM device attributes:
0 0 0 0 0 1 1 0 06
2, 3
CE latency
19
SDRAM device attributes:
0 0 0 0 0 0 0 1 01
0
S latency
Data Sheet E0085H10
6