HB52E649E12 Datasheet, PDF (6/16 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

HB52E649E12-A6B/B6B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
22
SDRAM device attributes:
General
0 0 0 0 1 1 1 0 0E
V_CC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6B) 10 ns
1 0 1 0 0 0 0 0 A0
CL = 2
*⁷
(-B6B) Undefined
0 0 0 0 0 0 0 0 00
24
SDRAM access from Clock
0 1 1 0 0 0 0 0 60
(2nd highest CE latency)
(-A6B) 6 ns
(-B6B) Undefined
0 0 0 0 0 0 0 0 00
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0 0 0 0 0 0 0 0 00
26
SDRAM access from Clock
0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
27
Minimum row precharge time 0 0 0 1 0 1 0 0 14
20 ns
28
Row active to row active min 0 0 0 1 0 1 0 0 14
20 ns
29
RE to CE delay min
0 0 0 1 0 1 0 0 14
20 ns
30
Minimum RE pulse width
0 0 1 1 0 0 1 0 32
50 ns
31
Density of each bank on module 1 0 0 0 0 0 0 0 80
1 bank
512M byte
32
Address and command signal 0 0 1 0 0 0 0 0 20
input setup time
2 ns*⁷
33
Address and command signal 0 0 0 1 0 0 0 0 10
input hold time
1 ns*⁷
34
Data signal input setup time
0 0 1 0 0 0 0 0 20
2 ns*⁷
35
Data signal input hold time
0 0 0 1 0 0 0 0 10
1 ns*⁷
36 to 61 Superset information
0 0 0 0 0 0 0 0 00
Future use
62
SPD data revision code
0 0 0 1 0 0 1 0 12
Rev. 1.2A
63
Checksum for bytes 0 to 62
0 0 1 0 0 0 1 1 23
35
(-A6B)
(-B6B)
0 0 1 0 0 0 0 1 21
33
64
Manufacturer’s JEDEC ID code 0 0 0 0 0 1 1 1 07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00
72
Manufacturing location
× × × × × × × × ××
*³ (ASCII-
8bit code)
73
Manufacturer’s part number
0 1 0 0 1 0 0 0 48
H
74
Manufacturer’s part number
0 1 0 0 0 0 1 0 42
B
75
Manufacturer’s part number
0 0 1 1 0 1 0 1 35
5
76
Manufacturer’s part number
0 0 1 1 0 0 1 0 32
2
Data Sheet E0020H20
6