HB52E649E12 Datasheet, PDF (10/16 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

HB52E649E12-A6B/B6B
DC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52E649E12
-A6B
-B6B
Parameter
Symbol Min Max Min Max Unit Test conditions Notes
Operating current
(CE latency = 3)
I _CC1
(CE latency = 4)
I _CC1
Standby current in power I_CC2P
down
Burst length = 1 1, 2, 3
—
2220 —
—
mA
t_RC = min
—
2220 —
2220 mA
—
564 —
564 mA
CKE = V_IL, t_CK = 12 6
ns
Standby current in power I_CC2PS
—
546 —
546 mA
CKE = V_IL, t_CK = ∞ 7
down (input signal stable)
Standby current in non I_CC2N
—
870 —
870 mA
CKE, S = V_IH,
4
power down
t_CK = 12 ns
Active standby current in I_CC3P
power down
—
582 —
582 mA
CKE = V_IL, t_CK = 12 1, 2, 6
ns
Active standby current in I_CC3N
non power down
Burst operating current
(CE latency = 3)
I _CC4
(CE latency = 4)
I _CC4
Refresh current
I _CC5
Self refresh current
I _CC6
Input leakage current
I _LI
Output leakage current I_LO
—
1050 —
1050 mA
—
2220 —
—
mA
—
2220 —
2220 mA
—
4470 —
4470 mA
—
564 —
564 mA
–10 10
–10 10
µA
–10 10
–10 10
µA
CKE, S = V_IH,
t_CK = 12 ns
t_CK = min, BL = 4
1, 2, 4
1, 2, 5
V_IH ≥ V_CC – 0.2 V
8
V_IL ≤ 0.2 V
0 ≤ Vin ≤ V_CC
0 ≤ Vout ≤ V_CC
DQ = disable
Output high voltage
V_OH
2.4 —
2.4 —
V
I_OH = –4 mA
Output low voltage
V_OL
—
0.4 —
0.4 V
I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Data Sheet E0020H20
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