HB52E649E12 Datasheet, PDF(13/16 Page) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

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HB52E649E12 Datasheet, PDF (13/16 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

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HB52E649E12-A6B/B6B

Relationship Between Frequency and Minimum Latency

Parameter

Frequency (MHz)

tCK (ns)

Active command to column command (same bank)

Active command to active command (same bank)

HB52E649E12

-A6B/B6B

PC100

Symbol Symbol 10

I RCD

I RC

Active command to precharge command (same bank) IRAS

Precharge command to active command (same bank) IRP

Write recovery or data-in to precharge command

I DPL

(same bank)

Tdpl 1

Active command to active command (different bank) IRRD

Self refresh exit time

I SREX

Tsrx

Last data in to active command

(Auto precharge, same bank)

I APW

Tdal 3

Self refresh exit to command input

I SEC

Precharge command to high impedance

(CE latency = 3)

I HZP

Troh 3

(CE latency = 4)

I HZP

Troh 4

Last data out to active command (auto precharge)

I APR

(same bank)

Last data out to precharge (early precharge)

I EP

â2

(CE latency = 3)

(CE latency = 4)

I EP

â3

Column command to column command

I CCD

Tccd 1

Write command to data in latency

I WCD

Tdwd 1

DQMB to data in

I DID

Tdqm 1

DQMB to data out

I DOD

Tdqz 3

CKE to CK disable

I CLE

Tcke 2

I RSA

Tmrd 1

S to command disable

I CDD

Power down exit to command input

I PEC

Notes: 1. IRCD to IRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

Notes

= [IRAS + IRP]

= [IDPL + IRP]

= [IRC]

Data Sheet E0020H20

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