HB52E649E12 Datasheet, PDF (12/16 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

HB52E649E12-A6B/B6B
AC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V) (cont)
HB52E649E12
-A6B/B6B
Parameter
PC100
Symbol Symbol Min
Max
Unit Notes
Command setup time
t _CS
Command hold time
t _CH
Ref/Active to Ref/Active command period t_RC
Active to precharge command period
t _RAS
Active command to column command t_RCD
(same bank)
Tsi
2.6
Thi
1.6
Trc
70
Tras
50
Trcd
20
—
ns
1
—
ns
1
—
ns
1
120000 ns
1
—
ns
1
Precharge to active command period
t _RP
Trp
20
—
ns
1
Write recovery or data-in to precharge t_DPL
Tdpl
10
—
ns
1
lead time
Active (a) to Active (b) command period t_RRD
Trrd
20
—
ns
1
Transition time (rise to fall)
t_T
1
5
ns
Refresh period
t _REF
—
64
ms
Notes: 1. AC measurement assumes t_T = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C_L = 50 pF.
3. t_LZ (min) defines the time at which the outputs achieves the low impedance state.
4. t_HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t_CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
input
2.4 V
2.0 V
0.4 V ^{0.8 V}
t_T
t_T
DQ
CL
Data Sheet E0020H20
12