HB54A2569F1U Datasheet, PDF (5/17 Pages) Elpida Memory – 256MB, 512MB Registered DDR SDRAM DIMM

HB54A2569F1U, HB54A5129F2U
Serial PD Matrix*¹
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256 bytes
2
Memory type
0 0 0 0 0 1 1 1 07H
SDRAM DDR
3
Number of row address
0 0 0 0 1 1 0 1 0DH
13
4
Number of column address
0 0 0 0 1 0 1 0 0AH
10
5
Number of DIMM banks
HB54A2569F1U
HB54A5129F2U
0 0 0 0 0 0 0 1 01H
1
0 0 0 0 0 0 1 0 02H
2
E₆
Module data width
0 1 0 0 1 0 0 0 48H
72 bits
7
Module data width continuation
0 0 0 0 0 0 0 0 00H
0 (+)
8
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
SSTL 2.5V
O₉
DDR SDRAM cycle time, CL = X
-A75B
0 1 1 1 0 0 0 0 70H
CL = 2.5*⁵
-B75B
0 1 1 1 0 1 0 1 75H
-10B
1 0 0 0 0 0 0 0 80H
L ¹⁰
SDRAM access from clock (tAC)
-A75B, -B75B
0 1 1 1 0 1 0 1 75H
0.75ns*⁵
-10B
1 0 0 0 0 0 0 0 80H
0.8ns*⁵
11
DIMM configuration type
0 0 0 0 0 0 1 0 02H
ECC
12
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8 µs
Self refresh
13
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
P ₁₄
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
×8
SDRAM device attributes:
15
Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01H
1 CLK
column access
r ₁₆
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
2, 4, 8
o ¹⁷
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
4
18
SDRAM device attributes:
/CAS latency
0 0 0 0 1 1 0 0 0CH
2, 2.5
19
SDRAM device attributes:
/CS latency
0 0 0 0 0 0 0 1 01H
0
d ₂₀
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02H
1
21
SDRAM module attributes
0 0 1 0 0 1 1 0 26H
Registered
u ²²
SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H
± 0.2V
Minimum clock cycle time at
23
CLX - 0.5
-A75B
0 1 1 1 0 1 0 1 75H
CL = 2*⁵
c ^-B75B/10B
1 0 1 0 0 0 0 0 A0H
Maximum data access time (tAC) from
24
clock at CLX - 0.5
0 1 1 1 0 1 0 1 75H
0.75ns*⁵
t ^{-A75B, -B75B}
-10B
1 0 0 0 0 0 0 0 80H
0.8ns*⁵
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00H
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00H
Data Sheet E0206H30 (Ver. 3.0)
5