HB54A2569F1U Datasheet, PDF (10/17 Pages) Elpida Memory – 256MB, 512MB Registered DDR SDRAM DIMM

HB54A2569F1U, HB54A5129F2U
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
SDRAM
PLL
stack
CK0
EOL _/CK0
OUT1
120Ω
IN
120Ω
OUT'N'
C
Feedback
120Ω
SDRAM
stack
240Ω _Register1
(Typically two registers per DIMM)
240Ω Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0 ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
P in a similar manner.
roduct ^{4. Termination resistors for feedback path clocks are located after the pins of the PLL.}
Data Sheet E0206H30 (Ver. 3.0)
10