EDJ5304BASE Datasheet, PDF (47/130 Pages) Elpida Memory – 512M bits DDR3 SDRAM

EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
26. For these parameters, the DDR3 SDRAM device is characterized and verified to support
tnPARAM [nCK] = RU{tPARAM [ns] / tCK(avg)}, which is in clock cycles, assuming all input clock jitter
specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will
support tnRP =RU{tRP / tCK(avg)} = 6, i.e. as long as the input clock jitter specifications are met, prechar
ge command at Tm and active command at Tm+6 is valid even if (Tm+6 − Tm) is less than 15ns due to
input clock jitter.
EOL^{27. These parameters should be the larger of the two values, analog (ns) and number of clocks (nCK).}
Product
Preliminary Data Sheet E0966E60 (Ver. 6.0)
47