EDJ5304BASE Datasheet, PDF (25/130 Pages) Elpida Memory – 512M bits DDR3 SDRAM

EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions for IDD2N, IDD2P (1), IDD2P (0) and IDD2Q
Symbol
IDD2N
IDD2P (1)*¹
IDD2P (0)*¹
IDD2Q
Name
Measurement Condition
Timing Diagram Example
ECKE
External Clock
tCK
O^tRC
tRAS
tRCD
L ^tRRD
Precharge standby
current
Figure IDD2N/IDD3N
Example
H
on
tCK min (IDD)
N/A
N/A
N/A
N/A
Precharge power-down Precharge power-down
current
current
Precharge quiet
(fast exit
(slow exit
standby current
MR0 bit A12= 1)
MR0 bit A12= 0)
⎯
L
on
tCK min (IDD)
N/A
N/A
N/A
N/A
⎯
L
on
tCK min (IDD)
N/A
N/A
N/A
N/A
⎯
H
on
tCK min (IDD)
N/A
N/A
N/A
N/A
CL
N/A
N/A
N/A
N/A
AL
N/A
N/A
N/A
N/A
/CS
Bank address,
row address and command
inputs
P _{Data inputs}
Output buffer DQ, DQS
/ MR1 bit A12
ODT
r / MR1 bits [A6, A2]
Burst length
H
STABLE
SWITCHING (see
Definition of SWITCHING STABLE
table)
SWITCHING
FLOATING
off / 1
disabled
/ [0,0]
N/A
off / 1
disabled
/ [0,0]
N/A
STABLE
STABLE
FLOATING
off / 1
disabled
/ [0,0]
N/A
H
STABLE
FLOATING
off / 1
disabled
/ [0,0]
N/A
o ^{Active banks}
none
none
none
none
Idle banks
all
all
all
all
Precharge Power-down
d _{Mode / MR0 bit A12}
N/A
Fast exit / 1
(any valid command
after tXP*²)
Slow exit / 0
Slow exit
(READ and ODT
N/A
commands must satisfy
tXPDLL-AL)
Notes: 1. In DDR3 the MR0 bit A12 defines DLL-on/off behaviors only for precharge power-down. There are two
u ^{different precharge power-down states possible: one with DLL-on (fast exit, bit A12 = 1) and one with}
DLL-off (slow exit, bit A12 = 0).
2. Because it is an exit after precharge power-down the valid commands are: bank activate (ACT), auto-
ct ^{refresh (REF), mode register set (MRS), self-refresh (SELF).}
Preliminary Data Sheet E0966E60 (Ver. 6.0)
25