EDJ5304BASE Datasheet, PDF (1/130 Pages) Elpida Memory – 512M bits DDR3 SDRAM

PRELIMINARY DATA SHEET
E ^{EEEDDDJJ5J55153332010M468BBBAAbASSiStEEsE((D(13622D48MMRMww3wooSorrdrdDdsssR}_×××^A₁₈₆₄^{Mbbbitiittsss)))} _{Specifications}
• Density: 512M bits
O_{• Organization}
⎯ 16M words × 4 bits × 8 banks (EDJ5304BASE)
⎯ 8M words × 8 bits × 8 banks (EDJ5308BASE)
L ^{⎯ 4M words × 16 bits × 8 banks (EDJ5316BASE)}
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
• Package
⎯ 78-ball FBGA (EDJ5304/5308BASE)
⎯ 96-ball FBGA (EDJ5316BASE)
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.5V ± 0.075V
• Data rate
P _{⎯ 1333Mbps/1066Mbps/800Mbps (max.)}
• 1KB page size (EDJ5304/5308BASE)
⎯ Row address: A0 to A12
⎯ Column address: A0 to A9, A11 (EDJ5304BASE)
r _{A0 to A9 (EDJ5308BASE)}
• 2KB page size (EDJ5316BASE)
o ⎯ Row address: A0 to A11
⎯ Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
d _{• Burst lengths (BL): 8 and 4 with Burst Chop (BC)}
• Burst type (BT):
⎯ Sequential (8, 4 with BC)
u ^{⎯ Interleave (8, 4 with BC)}
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
c access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
t ^{• Refresh: auto-refresh, self-refresh}
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
⎯ Synchronous ODT
⎯ Dynamic ODT
⎯ Asynchronous ODT
• Multi Purpose Register (MPR) for temperature read
out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset
function
• SRT range:
⎯ Normal/extended
⎯ Auto/manual self-refresh
• Programmable Output driver impedance control
• Refresh cycles
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Document No. E0966E60 (Ver. 6.0) _{This product became EOL in September, 2010.}
Date Published July 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007