EDJ5304BASE Datasheet, PDF (117/130 Pages) Elpida Memory – 512M bits DDR3 SDRAM

EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination
strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by
the “Dynamic ODT” feature as described as follows:
Functional Description:
The Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to ’1’. The function and is described as follows:
• Two RTT values are available: RTT_Nom and RTT_WR.
⎯ The value for RTT_Nom is pre-selected via bits A[9,6,2] in MR1
⎯ The value for RTT_WR is pre-selected via bits A[10,9] in MR2
E• During operation without write commands, the termination is controlled as follows:
⎯ Nominal termination strength RTT_Nom is selected.
⎯ Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
O^{• When a write command (WRIT, WRITA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is}
enabled, the termination is controlled as follows:
⎯ A latency ODTLcnw after the write command, termination strength RTT_WR is selected.
⎯ A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected
L ^{OTF) after the write command, termination strength RTT_Nom is selected.}
⎯ Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
Table Latencies and Timing Parameters Relevant for Dynamic ODT shows latencies and timing parameters, which
are relevant for the on-die termination control in Dynamic ODT mode:
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a write command is registered by the SDRAM
with ODT high, then ODT must remain high until ODTH4 (BC4) or ODTH8 (BL8) after the write command (see the
figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to
P ^{ODT registered low or from the registration of a write command until ODT is registered low.}
[Latencies and Timing Parameters Relevant for Dynamic ODT]
Parameters
Symbols
Defined from
Defined to
Definition for all DDR3
speed bins
r _{ODT turn-on Latency}
ODTLon
Registering external
ODT signal high
Turning termination on
ODTLon = WL – 2.0
o ^{ODT turn-off Latency}
ODTLoff
Registering external
ODT signal low
Turning termination off
ODTLoff = WL – 2.0
ODT latency for changing
from RTT_Nom to RTT_WR
ODTLcnw
Registering external
write command
Change RTT
RTT_Nom to
strength from
RTT_WR
ODTLcnw
=
WL
– 2.0
ODT latency for change
from RTT_WR to RTT_Nom
d _(BC4)
ODTLcwn4
Registering external Change RTT strength from ODTLcwn4 =
write command
RTT_WR to RTT_Nom 4 + ODTLoff
ODT latency for change
from RTT_WR to RTT_Nom
(BL8)
ODTLcwn8
Registering external Change RTT strength from ODTLcwn8 =
write command
RTT_WR to RTT_Nom 6 + ODTLoff
u _{Minimum ODT high time after}
ODT assertion
ODTH4
registering ODT high ODT registered low
ODTH4 (min.) = 4
Minimum ODT high time after
Write (BC4)
ODTH4
registering Write with
ODT high
ODT registered low
ODTH4 (min.) = 4
c ^{Minimum ODT high time after}
Write (BL8)
ODTH8
registering Write with
ODT high
ODT registered low
ODTH8 (min.) = 6
t ^{RTT change skew}
tADC
ODTLcnw
ODTLcwn
RTT valid
0.3ns to 0.7ns
Unit
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tCK (avg)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
117