HB52RF649DC Datasheet, PDF (12/16 Pages) Elpida Memory – 512MB Unbuffered SDRAM S.O.DIMM

HB52RF649DC-B, HB52RD649DC-B
Relationship Between Frequency and Minimum Latency
Parameter
-75
-A6
Frequency (MHz)
133
100
tCK (ns)
PC100
Symbol Symbol 7.5
10
Active command to column command
(same bank)
lRCD
3
2
Active command to active command
(same bank)
lRC
9
7
Active command to precharge command (same
bank)
lRAS
6
5
Precharge command to active command (same
bank)
lRP
3
2
Write recovery or data-in to precharge command
(same bank)
lDPL
Tdpl
2
2
Active command to active command
(different bank)
lRRD
2
2
Self refresh exit time
lSREX Tsrx
1
1
Last data in to active command
(Auto precharge, same bank)
lAPW
Tdal
5
4
Self refresh exit to command input
lSEC
9
7
Precharge command to high impedance
(CL = 2)
lHZP
Troh 2
2
(CL = 3)
lHZP
Troh 3
3
Last data out to active command
(Auto precharge, same bank)
lAPR
1
1
Last data out to precharge (early precharge)
(CL = 2)
lEP
–1
–1
(CL = 3)
lEP
–2
–2
Column command to column command
lCCD
Tccd 1
1
Write command to data in latency
lWCD
Tdwd 0
0
DQMB to data in
lDID
Tdqm 0
0
DQMB to data out
lDOD
Tdqz 2
2
CKE to CK disable
lCLE
Tcke 1
1
Register set to active command
lRSA
Tmrd 1
1
/S to command disable
lCDD
0
0
Power down exit to command input
lPEC
1
1
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Notes
1
= [lRAS+ lRP]
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Data Sheet E0223H30 (Ver. 3.0)
12