GD25D05B Datasheet, PDF (8/28 Pages) ELM Electronics – 512K-bit Serial Flash

GD25D05BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status
Register (WRSR) instruction is not execution. The default value of SRP is 0.
SRP #WP
Status Register
Description
0
×
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
1
0
Hardware Protected
WP#=0, the Status Register locked and can not be written
to.
1
1
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be
written to after a Write Enable command, WEL=1.
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device by the host system, with the most
significant bit first. On the first rising edge of SCLK after CS# is driven low, the one-byte command code must
be shifted into the device, with the most significant bit first on SI, each bit being latched on the rising edges of
SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or data bytes, or dummy bytes. CS# must be driven high after the last bit of
the command sequence has been shifted in.
For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read
Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after
any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,
which means the clock pulse number should be an exact multiple of eight. Otherwise the command is rejected to
executed. Especially for Page Program command, if at any time the input end is not a completed byte, nothing
will be written into the memory array, neither would WEL bit be reset.
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Rev.1.0