GD25D05B Datasheet, PDF (11/28 Pages) ELM Electronics – 512K-bit Serial Flash

GD25D05BxIGx Uniform sector dual and quad serial flash
Figure 3. Read Status Register Sequence Diagram
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CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
SI
05H
SO
High-Z
S7~S0 out
S7~S0 out
76543210765432107
MSB
MSB
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write
Enable (WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can
be accepted.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the
instruction code and the data byte on Serial Data Input (DI).
The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6
and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been
latched in. Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#)
is driven High, the self-timed Write Status Register cycle (the duration is tw) is initiated. While the Write Status
Register cycle is in progress, reading Status Register to check the Write in Progress (WIP) bit is achievable.
The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the
completion of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2,
BP1, BP0) bits, which are utilized to define the size of the read-only area.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect
(SRP) bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into
Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once enter
into the Hardware Protected Mode (HPM).
Figure 4. Write Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
Status Register in
SI
01H
76543210
SO
MSB
High-Z
28 - 11
Rev.1.0