GD25Q21 Datasheet, PDF (7/49 Pages) ELM Electronics – Uniform Sector Dual and Quad Serial Flash

GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Quad SPI
The GD25Q21B supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”, “Quad I/O Word Fast Read”, ”Quad Page Program” (6BH, EBH, E7H, 32H) commands. These
commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When
using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and
HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in
Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and
starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD
operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with
SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is
high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be
at high and then CS# must be at low.
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5. DATA PROTECTION
The GD25Q21B provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
- Erase Security Register / Program Security Register
♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the
memory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
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Rev.1.1