GD25Q21 Datasheet, PDF (6/49 Pages) ELM Electronics – Uniform Sector Dual and Quad Serial Flash

GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
3. MEMORY ORGANIZATION
http://www.elm-tech.com
GD25Q21B
Each device has
256K
1K
64
4/8
Each block has
64/32K
256/128
16/8
-
Each sector has
4K
16
-
-
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Uniform Block Sector Architecture
GD25Q21B 64K Bytes Block Sector Architecture
Block
Sector
64
3
-----
-----
47
2
-----
32
31
1
-----
16
15
0
-----
0
03F000H
-----
-----
02F000H
-----
020000H
01F000H
-----
010000H
00F000H
-----
000000H
Address range
03FFFFH
-----
-----
02FFFFH
-----
020FFFH
01FFFFH
-----
010FFFH
00FFFFH
-----
000FFFH
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q21B feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q21B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
49 - 6
Rev.1.1