GD25Q32 Datasheet, PDF (36/50 Pages) ELM Electronics – 3.3V Uniform Sector Dual and Quad Serial Flash

GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
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→ CS# goes high. The command sequence is shown in Figure35. CS# must be driven high after the eighth bit
of the command code has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.
While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the
Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP
protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the
Erase Security Registers command will be ignored.
Address
A23-A16
A15-A12
A11-A10
A9-A0
Security Register #1
00H
Security Register #2
00H
Security Register #3
00H
0001
0010
0011
00
Byte Address
00
Byte Address
00
Byte Address
Figure 35. Erase Security Registers command Sequence Diagram
CS#
SCLK
SI
0123456789
29 30 31
Command
44H
24 Bits Address
23 22
210
MSB
7.31. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 1024
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-A16
A15-A12
A11-A10
A9-A0
Security Register #1
00H
Security Register #2
00H
Security Register #3
00H
0001
0010
0011
00
Byte Address
00
Byte Address
00
Byte Address
50 - 36
Rev.1.0