MA31751 Datasheet, PDF (5/17 Pages) Dynex Semiconductor – Memory Management & Block Protection Unit

MA31751
2.0 TIMING CONSIDERATIONS
3.2 MPROEN
2.1 MMU TIMINGS
To enable a fast page register look-up time, the MMU has
two fast translation cache registers. These hold the address
translation information on the 4K memory page which is
currently being accessed. When the CPU has control of the
system, one cache register is for operand transfers and one for
instruction transfers, as these often occur in different pages.
The appropriate translation cache register is chosen by the
operand/instruction (OIN) signal from the CPU. When a DMA
has system control, the caches operate as Read/Write caches,
the appropriate cache being selected by the RDWN signal.
When either an instruction/read or an operand/write crosses a
page boundary, one wait state may be added whilst the
translation cache register is updated from internal memory.
This system minimises the MMU overhead.
This signal is always low when ASIN is low. On a memory
access, with an MMU only present it stays low until the
address translation is validated. If the translation is erroneous,
it stays low, causing a machine cycle time-out. If a BPU is
present with the MMU, an erroneous translation causes the
output to stay low. If the translation is correct, MPROEN will
still stay low until the BPU check has completed. If there is no
block protection set, MPROEN goes high, allowing the cycle to
proceed. If the block protection is set, MPROEN stays low and
the cycle times out. In a BPU only system, MPROEN indicates
whether or not the protection bit is set for the address being
accessed.
In a 1750B system with both an MMU and BPU present,
MPROEN may glitch between the translation validation and
the protection check (as the MMU and BPU functions may be
on different devices). In this case, MPROEN should be gated
with BPUVALIDN being low before being input to the CPU.
2.2 BPU TIMINGS
A similar caching system is employed in the BPU section
of the MA31751 to allow more rapid detection of access
violations. If the physical address crosses a 16K block
boundary, then one wait state may be added.
Different combinations of cache hits and misses give
different access times if the MA31751 is acting as both an
MMU and a BPU. If the logical address (from the CPU) gives
an MMU cache hit, the physical address is looked-up from the
translation cache register (operand or instruction, depending
on OIN). If the physical address gives a cache hit, the
protection for the block is looked-up in the BPU cache register.
This situation (both hits) gives the fastest access time. The
access time is a maximum if both logical and physical
addresses give cache misses.
3.0 OUTPUTS FROM THE MA31751
3.1 PRPEN
3.3 BPUVALIDN
BPUVALIDN falls to indicate that the output from the BPU
is valid. If no BPU is present, BPUVALIDN remains high.
4.0 PIN DESCRIPTIONS
A description of each pin function appears in Figure 6. The
acronym is presented first, followed by its function and
description. Timing characteristics of each of the functions are
shown in section 6.
All CMOS compatible signals are protected by an
Electrostatic Discharge (ESD) protection circuit. Throughout
this data sheet, active low signals are denoted either by
placing a bar over the signal name,or by following the signal
name with an “N” suffix, e.g.,DSN.
All unused inputs should be connected to their inactive
state and should not be allowed to float.
This signal goes active low if a parity error occurs on a
memory access, ie. there is a parity error in the MMU page
register. There is no parity checking on XIO cycles, (this
should be covered by the processor).
5/17