MA31751 Datasheet, PDF (4/17 Pages) Dynex Semiconductor – Memory Management & Block Protection Unit

MA31751
Logical
1750A
Addressing
Physical
AS[0:3]
AS0
AS3 A0
A[0:15]
EA3
PA0
EA[3:10]
EA10 A4
A[4:15]
1750A Extended Physical Address [0:19]
Logical*
PB[0:3]
PB0
PB3
AS[0:3]
AS0
AS3
A0
A[0:15]
1750B
Addressing
Physical
EA0
EA[0:10]
EA10 A4
A[4:15]
PA0
1750B Extended Physical Address [0:22]
* There are 16M words of logical address in 1750B. The 16MWord
logical to 8MWord physical mapping is user defined.
Figure 4: Extended Address Mapping in 1750A/B Mode
Addressable
Physical
Memory
64KW
1MW
64KW
1MW
64KW
8MW
8MW
8MW
8MW
8MW
64KW
8MW
8MW
8MW
8MW
8MW
Addressable
Logical
Memory
64KW
1MW
64KW
1MW
64KW
1MW
2MW
4MW
8MW
16MW
64KW
1MW
2MW
4MW
8MW
16MW
Is BPU
Protection
Required?
NO
NO
YES
YES
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
Mode
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
Number of
MMUs
0
1
0
1
0
1
2
4
8
16
0
1
2
4
8
16
Number of
BPUs
0
0
1
1
0
0
0
0
0
0
1
8
8
8
8
8
Number of
MA31751s
Required
0
1
1
1
0
1
2
4
8
16
1
8
8
8
8
16
Notes: 1. Memory is specified in terms of addressable instruction space.
2. It is assumed that the whole of the physical address space is used in 1750B - if this is not the
case the number of MA31751 chips may be reduced.
Figure 5: MA31751 Selection Chart for Varying Memory Requirements
A15
A15
PA19
A15
A15
PA22
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