MA31751 Datasheet, PDF (2/17 Pages) Dynex Semiconductor – Memory Management & Block Protection Unit

MA31751
1.0 DEVICE OPERATION
The MA31751 is an interface device designed to increase
the memory addressing capability of the MA31750 CPU. It is
user configurable as an MMU and/or a BPU conforming to the
MIL-STD-1750A and the proposed MIL-STD-1750B. The
MMU provides expanded addressing and full access lock/key
protection in both modes, together with write/execute
protection on 4K pages.
The BPU allows up to 1M words of memory to be protected
in 1K blocks (MlL-STD-1750A). Up to 8M words may be
protected by multiple MMU/BPU units (draft MIL-STD-1750B).
In 1750A mode, one MA31751 unit can act as both MMU
and BPU for the maximum 1M words of address space. In
1750B mode, up to 8 MA31751 units may be used to provide
the maximum BPU functions and up to 16 units for the
maximum MMU functions. For any given physical memory
location the MMU and BPU function may be split across two
MA31751 devices depending on the logical to physical
address mapping.
1.1 INITIALISATION
The MA31751 is initialised by the CPU when a system
reset occurs. Initially all mappings are set one to one to give a
linear 1M word logical to physical mapping. The BPU defaults
to no protection on a reset and requires 256 machine cycles
(AS pulsing) to set the internal BPU memory. The CPU
recognises the presence of the MMU/BPU by the setting of
appropriate bits in the configuration register. When the
configuration register is read, the MA31751 stores MMU, BPU,
parity and 1750 mode information internally. The CPU may
change the mapping and access protection when it is in
privileged instruction mode using XIO commands 4D00 to
52FF as defined in MIL-STD-1750.
1.2 ADDRESS TRANSLATION AND PROTECTION
The MMU maps system memory into 4K word pages by the
mechanism shown in figure 3. A page is a block of physical
memory which is uniquely specified by the physical page
address, the PPA. A given address within any page is specified
by the least significant 12 bits of the CPU address bus. One
page register has the physical page address and the access
control information relating to one page. There are 512 page
registers, organized into 16 sets. The 16 sets are addressed by
AS[0:3]. Each set has two groups of page registers, one for
operand memory space and one for instruction memory space.
These are addressed by OIN. Each group contains 16 page
registers accommodating a total of 256 registers for each of
operand and instruction memory space.
The MMU also checks for protection violation by
comparing the processor state (PS), read from the CPU status
word, with the access lock (AL) field in the page register. An
additional bit in each page register allows the system to
disable writes to operand pages or reads (execution) of
instruction pages. If any memory violation occurs, the memory
protect output (MPROEN) is asserted low. This typically
causes a bus-fault-timeout on the processor which aborts the
error cycle.
Figure 2 illustrates the Access Key mapping mechanism.
When memory transactions are controlled by the MA31750,
the AS[0:3] and PS[0:3] bits necessary to perform the address
translation and access protection functions respectively, are
obtained from a copy of the processor status word held by the
MMU. Modifications to the CPU status word are reflected in the
MMU copy.
Figure 4 illustrates the standard way to map the logical
CPU addresses, AS[0:3] and PB[0:3] onto the physical
extended address bus for both 1750A (a 20-bit physical
address) and for 1750B (a 23-bit physical address). Figure 5
shows the various selections to achieve the required memory
size and protection.
AL Code
Acceptable Access Key Codes
0
0
1
0,1
2
0,2
3
0,3
4
0,4
5
0,5
6
0,6
7
0,7
8
0,8
9
0,9
A
0,A
B
0,B
C
0,C
D
0,D
E
0,E
F
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Figure 2: Access Lock and Key Mapping
1.3 BLOCK PROTECTION
The presence of a BPU in the system is determined from
the CPU configuration word. A BPU present in the system
offers protection of the physical memory in 1k blocks. It takes
the physcial address from the EA bus hence the BPU
protection cannot start until the MMU lookup has completed
and EAS rises. If no MMU is present, the physical address is
read from the processor address bus. The address selects the
relevant 16 bit word from the BPU RAM or cache. Each bit in
this word represents the protection on 1k of physical memory.
Any attempt to write a protected block results in an access
violation error from the BPU.
NOTE: MIL-STD-1750 states that the MSB of the Block
Protect Register (BPR) should protect the least significant
address block.
1.4 DIRECT MEMORY ACCESS
The MA31751 supports DMA access within the expanded
memory space, including translation and protection. When a
DMA controller is performing memory transactions, it must
provide the AS[0:3] and PS[0:3] signals to the inputs of the
MMU for address translation and access protection.
2/17