MA17503 Datasheet, PDF (25/34 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Interrupt Unit

No. Parameter
Test
Conditions⁽¹⁾⁽²⁾
Min
1
SYNCLKN ↓ to Data Valid
Load 1
-
2
Data Valid after SYNCLKN ↓
Load 1
30
3
SYNCLKN ↑ to IRDYN Valid
Load 1
-
4
IRDYN Valld after SYNCLKN ↓
Load 1
10
5
SYNCLKN ↓ to IRN Valid
Load 1
-
6
IRN Valid after SYNCLKN ↓
Load 1
15
7
SYNCLKN ↓ to PIFN Valid
Load 1
-
8
PIFN Valld after SYNCLKN ↓
Load 1
15
9
SYNCLKN ↓ to SURE, NPU, PAUSEN Valid
Load 1
-
10 SURE, NPU, ILLADN, PAUSEN after SYNCLKN ↓
Load 1
15
11 SYNCLKN ↓ to ILLADN ↑
Load 1
-
12 TCLK ↓ to ILLADN ↓ (Bus Timeout)
Load 1
-
13 EXADEN to ILLADN Valid
Load 1
-
14 TCLK ↓ to IRDYN ↓ (Bus Timeout)
Load 1
-
15 SYNCLKN ↑ to CONFWN Valid
Load 1
-
16 CONFWN Valid After SYNCLKN ↓
Load 1
10
17 SYNCLKN ↓ to DMAEN Valid
Load 1
-
18 DMAE Valid after SYNCLKN ↓
Load 1
5
19 SYNCLKN ↓ to DMAKN Valid
Load 1
-
20 DMAKN Valid after SYNCLKN ↓
Load 1
5
21 DTIMERN ↓ to DMAEN ↓
Load 1
-
22 DTIMERN ↓ to DMAEN ↑
Load 1
-
23 DTIMERN Setup to SYNCLKN ↓
50
24 DTIMERN Hold after SYNCLKN ↓
10
25 DTIMERN Setup to TGCLK ↑
30
26 DTIMERN Hold after TGCLK ↓
12
27 TGCLK ↓ to TGON ↓
Load 1
-
28 SYNCLKN ↑ to TGON ↑
Load 1
-
29 TGON Valid after SYNCLKN ↑
Load 1
15
30 DSN ↓ to DDN ↓
Load 1
10
31 DSN ↑ to DDN ↑
Load 1
10
32 DMAKN to DDN, CDN Valid
Load 1
-
33 HLDAKN to DDN, CDN Valid
Load 1
-
34 DMARN Setup to SYNCLKN ↓
20
35 DMARN Hold after SYNCLKN ↓
10
36 DTON Setup to TCLK ↓
30
37 DTON Hold after TCLK ↓
10
38 Address/Command Setup to SYNCLKN ↑
50
39 Address/Command Hold after SYNCLKN ↑
10
40 Data Setup to SYNCLKN ↓
50
41 Data Hold after SYNCLKN ↓
5
42 Microcode Setup to SYNCLKN ↓
10
43 Microcode Hold after SYNCLKN ↓
20
44 Interrupts Setup to SYNCLKN ↓
20
45 Interrupts Hold after SYNCLKN ↓
10
46 Faults Setup to SYNCLKN ↓
20
47 Faults Hold after SYNCLKN ↓
15
48 Bus Fault Timeout Interval (4)
1
49 INTREN Setup to SYNCLKN ↓
30
50 INTREN Hold after SYNCLKN ↓
5
51 M/ION Setup to SYNCLKN ↓
40
52 M/ION Hold after SYNCLKN ↓
5
53 HLDAKN Setup to SYNCLKN ↓
20
54 HLDAKN Hold after SYNCLKN ↓
7
55 TCLK Setup to SYNCLKN ↓
15
56 TCLK Hold after SYNCLKN ↓
10
Mil-Std-883, Method 5005, Subgroups 9, 10, 11.
(1) T_A = +25°C, -55°C and +125°C tested at V_DD = 4.5V and 5.5V.
(2) Unless otherwise noted: VIL ≥ 0.9V, VIH ≤ 4.0V timing measured from 50% to 50% points.
(3) r = 1OSC period 0.5r implies 50% OSC duty cycle.
(4) Data obtained by characterization or analysis; not routinely measured.
Table 7b: Timing Parameter Values
MA17503
Typ
Max⁽³⁾
Units
3r+100
-
40
-
60
-
50
-
50
-
75
75
60
50
75
-
75
-
50
-
60
60
-
-
-
-
150
75
-
35
35
30
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK
ns
ns
ns
ns
ns
ns
ns
ns
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