AP9050 Datasheet, PDF (6/9 Pages) Diodes Incorporated – PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL

Applications Information
Theory of Operation
The AP9050 was designed to work in close relationship
with a PMIC (Power Management IC). To protect the
PMIC from an overvoltage situation the AP9050 powers up
a detection circuit within the connected PMIC. (See Figure
2 as reference)
This detection circuit determines if a valid input source is
connected (ex. V_IN < 8V). If a valid input source is detected
the power MOSFET will be turned on and the supply
current to the PMIC will be turned on. The overvoltage
detection is continuous, if an overvoltage occurs at a later
state the Power MOSFET will be turned off.
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
External Capacitors
AP9050 was specified to reduce board space and external
component count, by designing the LDO to be stable
without an external bypass capacitor.
A low ESR 1nF to 10nF external capacitor can be used to
improve behavior with fast ac transients or other switching
currents that might be present.
To improve noise immunity and ac impedance from long
input traces a 1nF capacitor can be added to the input V_IN
of the LDO.
PCB Layout
The AP9050 was designed utilizing two process
technologies to provide best performance and a cost
effective solution.
1
6
8
2
5
7
3
4
Figure 6. Package Pin Out
Both die are packaged side by side in the U-DFN2020-6
package and are mounted on two separate exposed pads.
These pads are not required for electrical functionality, but
to aid with the thermal performance of AP9050.
Attention should be paid in the layout of the PCB (Printed
Circuit Board) that PAD7 is connected to V_IN of the LDO,
pin 3, while PAD8 is connected to the Drain of the Power
MOSFET, pin 6 of the package. For best thermal
performance large copper areas connected to the two
exposed pads should be used to transfer heat away from
the AP9050.
AP9050
Document number: DS35283 Rev. 1 - 2
6 of 9
www.diodes.com
March 2011
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