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| AP9050 Datasheet, PDF (4/9 Pages) Diodes Incorporated – PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL | |||
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AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Electrical Characteristics (VIN (OVP_SENSE) = 5.0V, TJ = +25°C, unless otherwise noted)
Symbol
Parameter
Test Conditions
Power FET
IDSS
IGSS
VGS(th)
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
Gate Threshold Voltage
VDS = 24V, VGS = 0V
TJ = 85°C
VDS = 0V, VGS = ±8V
VGS = VDS, ID = 250µA
RDS(on)
gFS
CISS
Drain-to-Source On-Resistance
(Note 7)
Forward Transconductance
Input Capacitance
VGS = 4.5V, ID = 2.0A
VGS = 2.5V, ID = 2.0A
VDS = 5V, ID = 2.0A
VDS = 15V, VGS = 0V,
f = 1MHz
COSS
Output Capacitance
VDS = 15V, VGS = 0V,
f = 1MHz
CRSS
Reverse Transfer Capacitance
VDS = 15V, VGS = 0V,
f = 1MHz
LDO (unless otherwise noted, TJ = 25ºC, VIN = 5.0V)
VOUT
Regulated Output Voltage
VIN = 5.5V, IOUT = 1mA
Vhead
Headroom
VIN â VOUT, IOUT = 1.2mA,
VIN = 4.6V
VIN â VOUT, IOUT = 10mA,
VIN = 4.8V, TJ = â40 to +125°C
Response to Input Transient
tpulse
Time signal is above 5.5V
VIN 0 to 30V, < 1µs rise time,
5.0k⦠resistive load (Note 8)
Vpk
Peak Voltage
VIN 0 to 30V, < 1µs rise time,
5.0k⦠resistive load (Note 8)
Total Device
Ibias
Input Bias Current
VIN = 5.5V
VIN_min Minimum Operating Voltage
Notes:
7. Pulse test width 300µs, duty cycle 2%
8. Guaranteed by design
Min
0.62
4.6
Typ.
0.9
41
55
8
500
65
50
5.0
110
Max
1.0
10
80
1.2
53
68
5.3
150
1000
5.0
9.0
850
3.0
Unit
µA
nA
V
mâ¦
S
pF
pF
pF
V
mV
mV
µs
V
µA
V
AP9050
Document number: DS35283 Rev. 1 - 2
4 of 9
www.diodes.com
March 2011
© Diodes Incorporated
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