AP9050 Datasheet, PDF (2/9 Pages) Diodes Incorporated – PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL

AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Pin Descriptions
Pin #
1
2
3, 7
4
5
6, 8
Name
Source
Gate
V_IN
Ground
V_OUT
Drain
Description
Source of the n-channel power FET. Pass-switch’s output pin.
Gate of the FET switch. Pass-switch’s control pin.
Input voltage to the internal LDO.
LDO ground connection.
Output of the LDO.
Drain of the power FET. Pass-switch’s input pin.
Functional Block Diagram
Figure 2. Functional Block Diagram
AP9050
Document number: DS35283 Rev. 1 - 2
2 of 9
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March 2011
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