DA9053 Datasheet, PDF (69/183 Pages) Dialog Semiconductor – Flexible High-Power System PMIC with Switching USB Power Manager

DA9053
Flexible High-Power System PMIC with 1.8 A
Switching USB Power Manager
In order to allow the host to determine the reason for the RESET a FAULTLOG register records the
cause.
When returning from POWER-DOWN mode the RESET mode will be achieved after powering down
domain SYSTEM completely and continue towards a state with absolute minimum current
consumption, with the only active circuits being LDOCORE, the BCD counter, the band gap and the
VDD_REF, VBUS, DCIN, ACC_ID_DET and VDDOUT comparators. Beside supplies (controlled by
the power sequencer) and the backup battery charger, other blocks on DA9053 (for example the
backlight boost) are automatically disabled to avoid draining the battery. During DA9053 RESET
mode the host processor can be held in a RESET state via port nRESET that is always asserted to
low when DA9053 progresses from RESET mode (for example after cold start from NO-POWER
mode) and can be asserted (depending on configuration of sequencer step 0) when the sequencer
has finished powering down domain SYSTEM (even partially) .
Some RESET conditions like the SHUTDOWN via register bit, WATCHDOG error, or over-
temperature, will automatically expire. Other conditions like asserting the port nSHUTDOWN need to
be released to enable a progression from RESET to POWER-DOWN mode. If the RESET was
initiated by the user a 500 ms time out will be inserted before trying to power up again. When the
RESET condition has disappeared DA9053 requires either a connected good main battery (V_DDOUT >
V_{DD_FAULT_UPPER}) or a detected supply (VBUS/DCIN > VCH_THR) that is able to provide enough
power to VDDOUT (V_DDOUT > V_{DDOUT_MIN}) to start up to POWER-DOWN mode.
11.4 NO-POWER Mode
DA9053 will enter the NO-POWER mode when the internal supply rail V_{DD_REF} drops below
V_{POR_LOWER} (for example during continued discharge of main and backup battery). As long as V_{DD_REF}
is now lower than V_{POR_UPPER} the core supply LDOCORE, the 32K oscillator and the BCD counter are
switched off, an internal power-on-reset (nPOR) is asserted and only the VDD_REF comparator is
active and checks for a condition that allows DA9053 to turn on again. When DA9053 detects either
a good main battery or a connected supply charger which raises V_{DD_REF} > V_{POR_UPPER} it will reset the
BCD counter and progress to RESET mode.
11.5 Power Commander Mode
This is a special mode for evaluation and configuration. In power commander mode DA9053 is
configured to load the control register default values from the HS 2-wire interface instead of from the
OTP cells so that unprogrammed DA9053 samples will power up and allow a PC running power
commander software to load all the configuration registers.
Power commander mode is enabled by connecting TP to VDDCORE.
In RESET mode DA9053 will do an initial OTP read to setup the trim values. However, if the OTP
values loaded into these registers are not as required they can be updated during the subsequent
power commander programming sequences.
NOTE
In power commander mode GPI14/15 will be configured for HS-2-wire interface operation (with VDDCORE as
the supply) and GPO13 will be configured as an output for nVDD_FAULT. Any register writes or OTP loads
which can change this configuration are ignored until DA9053 has exited from power commander mode.
After the initial OTP read has completed DA9053 informs the system that it is waiting for a
programming sequence by driving nVDD_FAULT low. The software running on the PC monitors
nVDD_FAULT and responds by downloading the values into the configuration registers within
DA9053. nVDD_FAULT is automatically released after the release register is loaded.
There are two programming sequences performed in power commander mode. The first takes place
between RESET and POWER-DOWN mode and the second takes place between POWER-DOWN
and SYSTEM mode. Two release registers are used support these two programming sequences:
Datasheet
CFR0011-120-00
Revision 2.1
69 of 183
31-Aug-2016
© 2016 Dialog Semiconductor