DA9053 Datasheet, PDF (68/183 Pages) Dialog Semiconductor – Flexible High-Power System PMIC with Switching USB Power Manager

DA9053
Flexible High-Power System PMIC with 1.8 A
Switching USB Power Manager
11 Operating Modes
11.1 ACTIVE Mode
DA9053 enters ACTIVE mode after the host processor has performed at least one initial ‘alive’
watchdog write (or alternatively an initial assertion of the KEEP_ACT pin) within the target time
window (this watchdog condition can be disabled).
A running application is typically in ACTIVE mode. In this mode the PMIC core functions (for example
LDOCORE, BCD counter, internal oscillator) as well as a supplies for features like battery charger
and GP-ADC are enabled. In ACTIVE mode the host processor can take over the control of the
automatic battery charging block if necessary and is able to respond to any faults that have been
detected. Status information can be read from the host processor via the power manager bus and the
DA9053 can flag interrupt requests to the host via a dedicated interrupt port (nIRQ). Temperature
and voltages inside and outside the DA9053 can be monitored and any fault conditions flagged to the
host processor.
11.2 POWER-DOWN Mode
DA9053 is in POWER-DOWN mode whenever the power domain SYSTEM is disabled (even
partially). This can be achieved when progressing from RESET mode or by returning from ACTIVE
mode. A return from ACTIVE mode is initiated by low-power mode instructions from the host or
happens as an interim state during an application shutdown to RESET mode.
During POWER-DOWN mode the LDOCORE, the band-gap, the nONKEY and the BCD counter are
active. In addition GPIO-ports, the GP-ADC, battery charger and the control interfaces keep on
running if not disabled. Also dedicated power supplies can be enabled in POWER-DOWN mode if
power down voltages have been pre-configured during ACTIVE mode. The internal oscillator (2 MHz)
will only run on demand (for example for a running GP-ADC or bucks that are enabled and are not
forced to PFM mode). The application supervision by WATCHDOG timer is discontinued in POWER-
DOWN mode. The digital control logic of disabled features of DA9053 (regulators, bucks, chargers,
boosts, GP-ADC, and others) will be disconnected from the clock tree via clock gating, so that the
device offers an optimized dissipation power in POWER-DOWN mode.
Following the next Wake-up event all supplies are re-configured with their default voltage values from
OTP and the sequencer timers are set to their default OTP values. If the POWER-DOWN mode was
caused by releasing SYS_EN the sequencer pointer is located at position 0 this allows default
enabling/disabling of supplies (beside LDOCORE).
11.3 RESET Mode
DA9053 is in RESET mode whenever a complete application reset is required. The RESET mode
happens after cold start when progressing from NO-POWER mode or can be forced by the user via a
pressed reset switch that is connected to port nSHUTDOWN, a long press of nONKEY (if its RESET
feature was enabled) or a long parallel assertion of GPIO14 and GPIO15 (if this RESET feature was
enabled), from the host processor by asserting port nSHUTDOWN or via an error detection from
DA9053.
DA9053 error conditions that force a RESET mode:
● A watchdog write from the host outside of the watchdog time window (if watchdog was enabled)
● An under-voltage detected at VDDOUT (V_DDOUT < V_{DD_FAULT_LOWER})
● An internal die over-temperature detected
● An over voltage or over current at the boost
Datasheet
CFR0011-120-00
Revision 2.1
68 of 183
31-Aug-2016
© 2016 Dialog Semiconductor