DA9053 Datasheet, PDF (60/183 Pages) Dialog Semiconductor – Flexible High-Power System PMIC with Switching USB Power Manager

DA9053
Flexible High-Power System PMIC with 1.8 A
Switching USB Power Manager
only for severe and unrecoverable hardware or software problems, because it completely resets the
processor and can result in data loss.
9.4 Reset Output (nRESET)
The nRESET signal is an active-low output signal from DA9053 to the host processor, which tells the
host to enter the hardware-reset state. nRESET is always asserted at the beginning of a DA9053
cold start from NO-POWER mode to when the DA9053 returns to RESET mode. nRESET can also
be asserted as a soft reset after the sequencer finishes powering down without progressing to
RESET mode.
The reset timer trigger signal can be configured to be EXT_WAKEUP, SYS_UP or PWR1_UP. After
being asserted nRESET remains low until the reset timer is started from the selected trigger signal
and expires. The expiry time can be configured from 1 ms to 1024 ms.
9.5 Accessory and ID Detect (ACC_ID_DET)
In ACTIVE and POWER-DOWN modes the detector can track the condition of the USB ID line and
differentiates between the following three conditions:
ACC_ID_DET:
● Floating (USB peripheral device connected)
● Shorted to ground (USB host device connected)
● Connected to ground via resistor (accessory asserted)
If the ACC_ID_DET pin stops floating (falling edge) during POWER-DOWN mode a wake up is
triggered.
9.6 System Enable (SYS_EN)
SYS_EN is an input signal from the host processor to DA9053 which initiates enabling the system
power supplies. The control SYS_EN will be initialized from OTP if the related port is configured as
GPI or GPO. The register bit SYS_EN can be read and changed via the control interfaces. DA9053
will not accept any power mode transition commands until the sequencer has stopped processing
IDs. De-asserting SYS_EN informs the DA9053 that the host processor is going into a
standby/hibernate mode. When the port is changing from active to passive state there is no IRQ or
wake-up event trigger. With the exception of supplies that are configured in ACTIVE mode with a
voltage preset before powering down all regulators and buck converters in power domain POWER1,
POWER and SYSTEM will be sequentially disabled in reverse order.
9.7 Power Enable (PWR_EN)
PWR_EN is an input signal from the host processor to DA9053 or is configured via OTP or host
commands. Initialisation, IRQ assertion and register bit PWR_EN control is similar to SYS_EN. To
ensure the correct sequencing SYS_EN has to be active before asserting PWR_EN. When de-
asserting SYS_EN the sequencer will sequentially power down POWER1, POWER and SYSTEM
domains respectively.
9.8 Power1 Enable (PWR1_EN)
PWR1_EN is an input signal from a host to DA9053 and is configured via OTP or host commands.
Initialisation, IRQ assertion and register bit PWR1_EN control is similar to SYS_EN. The domain
POWER1 is a sub power domain for general purpose.
Datasheet
CFR0011-120-00
Revision 2.1
60 of 183
31-Aug-2016
© 2016 Dialog Semiconductor