DA9061_17 Datasheet, PDF (42/82 Pages) Dialog Semiconductor – PMIC for applications requiring up to 6 A

DA9061
PMIC for applications requiring up to 6 A
6.9.1 Sub-Sequences
As illustrated in Figure 18, the sequencer is partitioned into three sub-sequences. These three sub-
sequences can be used to define three power modes for the target application and to move between
them in a controlled sequence as a response to control signals or register writes.
The first sub-sequence starts from step 0 and ends at a step defined by the SYSTEM_END pointer.
After the power-up is triggered, DA9061 performs a partial OTP read (OTP_RD2) if OTPREAD_EN is
set. It then waits for control SYSTEM_EN to trigger the first sub-sequence. If SYSTEM_EN is already
set in the OTP the first sub-sequence starts automatically after the power-up trigger. Alternatively,
SYSTEM_EN can be asserted through the SYS_EN input. When the sequencer reaches the
SYSTEM_END step the first sub-sequence is completed and the sequencer starts waiting for control
POWER_EN to trigger the second sub-sequence. If POWER_EN is already set in the OTP, the
sequencer does not stop after the first sub-sequence. Alternatively, POWER_EN can be asserted
through the PWR_EN input or via a register access.
The second sub-sequence starts from the step following SYSTEM_END and stops at a step defined
by the POWER_END pointer. When the sequencer reaches the POWER_END step (and the
watchdog is active), DA9061 enters ACTIVE mode. The final sub-sequence is triggered by asserting
POWER1_EN via a register write. The third sub-sequence starts from the step following
POWER_END and stops at a step defined by the MAX_COUNT pointer. If MAX_COUNT points to an
earlier step than SYSTEM_END or POWER_END the remaining steps of the sequencer are
disabled.
The power-down sequences are executed in reverse order to the power-up sequences. If the power-
down sequence is triggered from the ACTIVE mode by de-asserting POWER_EN, the sequencer
stops after reversing to the SYSTEM_END step. However, if the power-down sequence is triggered
by de-asserting SYSTEM_EN, the sequencer does not stop and reverses back to step 0.
Furthermore, if the power-down sequence is triggered by a watchdog timeout, the sequencer
reverses to step 0 immediately.
A partial power-down can be achieved by setting control STANDBY. This makes the sequencer stop
at the step pointed to by the PART_DOWN pointer. The next power-up will then start from the
PART_DOWN step, instead of step 0. The PART_DOWN pointer has to point to a step smaller than
the SYSTEM_END pointer.
6.9.2 Regulator Control
Each of DA9061’s buck converters and LDOs can be assigned to any of the sequencer steps. In
general, when the sequencer reaches a step to which a regulator is assigned, that regulator is
enabled by the sequencer. Likewise, when the sequencer reaches the same step on the way down,
the regulator is disabled. Multiple supplies can point to the same counter step, however, enabling
multiple regulators in the same slot can lead to increased in-rush currents.
In the simplest scheme, the sequencer enables regulators during a power-up, and disables them
during a power-down. This functionality is achieved by setting BUCK<x>_AUTO/LDO<x>_AUTO and
clearing BUCK<x>_CONF/LDO<x>_CONF. Alternatively, the sequencer can be configured to keep
the regulator enabled, but switch between the A and B settings in ACTIVE and POWERDOWN
modes. The functionality of the BUCK<x>_AUTO/LDO<x>_AUTO and
BUCK<x>_CONF/LDO<x>_CONF controls is summarized in Table 23.
Datasheet
CFR0011-120-00
Revision 3.3
42 of 82
04-Apr-2017
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