DR8051XP Datasheet, PDF (9/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

PERFORMANCE
The following tables give a survey about the
Core area and performance in ASICs Devices
(all key features have been included):
Device
Optimization
0.25u typical
area
F_max
100 MHz
0.25u typical
speed
200 MHz
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR8051XP clock periods} required to execute
an identical function. More details are available
in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
7,20
6,00
6,00
7,20
7,20
6,00
6,00
7,20
10,67
9,60
7,20
7,64
9,75
7,20
7,43
9,04
7,58
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DR8051XP per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
Target
Clock
frequency
Dhry/sec
(VAX MIPS)
80C51
-
12 MHz
268 (0.153)
80C310
-
33 MHz 1550 (0.882)
DR8051XP
0.25u
200 MHz 36996 (21.000)
Core performance in terms of Dhrystones
40000
35000
30000
25000
20000
15000
10000
5000
0
36996
268 ¹⁵⁵⁰
80C51 (12MHz)
DR8051XP (200MHz)
80C310 (33MHz)
Area utilized by the each unit of DR8051XP
core in vendor specific technologies is summa-
rized in table below.
CPU*
Component
Area
[Gates]
[FFs]
4900
220
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
Power Management Unit
300
32
100
-
100
-
50
8
100
10
500
40
350
25
50
5
I/O ports
400
35
Timers
600
50
Timer 2
600
60
UART0
700
60
UART1
700
60
Master I2C Unit
Slave I2C Unit
900
120
550
70
SPI Unit
Compare Capture Unit
450
55
550
60
Watchdog Timer
Multiply Divide Unit
400
45
1700
105
Total area
14000 1060
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
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