DR8051XP Datasheet, PDF (6/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

prgdatao[7:0]
prgdataz
prgrd
prgwr
xramdatao[7:0]
xramdataz
xramaddr[23:0]
xramrd
xramwr
docddatao
docdclk
pmm
stop
port0o[7:0]
port1o[7:0]
port2o[7:0]
port3o[7:0]
rxd0o
txd0
rxd1o
txd1
msclo
msclhs
msdao
msclo
msdao
sso[7:0]
so
mo
scko
sckz
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
Output data bus for Program Memory
PRGDATA tri-state buffers control line
Program Memory read
Program Memory write
Data bus for External Data Memory
XDATA tri-state buffers control line
External Data Memory address bus
External Data Memory read
External Data Memory write
DoCD™ data output
DoCD™ clock line
Power management mode indicator
Stop mode indicator
Port 0 output
Port 1 output
Port 2 output
Port 3 output
Serial receiver output 0
Serial transmitter line 0
Serial receiver output 1
Serial transmitter line 1
Master I2C clock output
High speed Master I2C clock line
Master I2C data output
Slave I2C clock output
Slave I2C data output
SPI slave select lines
SPI slave output
SPI master output
SPI clock output
SPI clock line tri-state buffer control
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UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module. Program fetch cycle length
can be programmed by user. This feature is
called Program Memory Wait States, and al-
lows core to work with different speed program
memories.
External Memory Interface – Contains mem-
ory access related registers such as Data
Pointer High (DPH0, DPH1), Data Pointer Low
(DPL0, DPL1), Data Page Pointer (DPP0,
DPP1), MOVX @Ri address register (MXAX)
and STRETCH registers. It performs the mem-
ory addressing and data transfers. Allows ap-
plications software to access up to 16 MB of
external data memory. The DPP0, DPP1 reg-
isters are used for segments swapping.
STRETCH register allows flexible timing man-
agement while accessing different speed sys-
tem devices by programming XRAMWR and
XRAMRD pulse width between 1 – 8 clock pe-
riods.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
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