DR8051XP Datasheet, PDF (1/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

DR8051XP
High Performance Configurable
8-bit Microcontroller
ver 3.10
OVERVIEW
DR8051XP is a high performance, area
optimized soft core of a single-chip 8-bit em-
bedded controller dedicated for operation with
fast (typically on-chip) and slow (off-chip)
memories. The core has been designed with a
special concern about low power consump-
tion. Additionally an advanced power man-
agement unit makes DR8051XP core perfect
for portable equipment where low power
consumption is mandatory.
DR8051XP soft core is 100% binary-
compatible with the industry standard 8051 8-
bit microcontroller. There are two configura-
tions of DR8051XP: Harward where external
data and program buses are separated, and
von Neumann with common program and ex-
ternal data bus. DR8051XP has RISC architec-
ture 6.7 times faster compared to standard
architecture and executes 65-200 million in-
structions per second. This performance can
also be exploited to great advantage in low
power applications where the core can be
clocked up to seven times more slowly than
the original implementation for no performance
penalty.
DR8051XP is fully customizable, which
means it is delivered in the exact configuration
to meet users’ requirements. There is no need
to pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC de-
sign flow.
CPU KEY FEATURES
● 100% software compatible with industry
standard 8051
● RISC architecture enables to execute in-
structions 6.7 times faster compared to
standard 8051
● 12 times faster multiplication
● 9.6 times faster division
● 2 Data Pointers (DPTR) for faster memory
blocks copying
○ Advanced INC & DEC modes
○ Auto-switch of current DPTR
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 64K bytes of Program Memory
● Up to 16M bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.