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DR8051XP Datasheet, PDF (2/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10 | |||
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â De-multiplexed Address/Data bus to allow
easy connection to memory
â Interface for additional Special Function
Registers
â Fully synthesizable, static synchronous de-
sign with positive edge clocking and no in-
ternal tri-states
â Scan test ready
â 1.3 GHz virtual clock frequency in a 0.35u
technological process
PERIPHERALS
â DoCD⢠debug unit
â Processor execution control
â Run
â Halt
â Step into instruction
â Skip instruction
â Read-write all processor contents
â Program Counter (PC)
â Program Memory
â Internal (direct) Data Memory
â Special Function Registers (SFRs)
â External Data Memory
â Hardware execution breakpoints
â Program Memory
â Internal (direct) Data Memory
â Special Function Registers (SFRs)
â External Data Memory
â Hardware breakpoints activated at a certain
â Program address (PC)
â Address by any write into memory
â Address by any read from memory
â Address by write into memory a required data
â Address by read from memory a required data
â Three wire communication interface
â Power Management Unit
â Power management mode
â Switchback feature
â Stop mode
â Extended Interrupt Controller
â 2 priority levels
â Up to 7 external interrupt sources
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are trademarks of their respective owners.
â Up to 8 interrupt sources from peripherals
â Four 8-bit I/O Ports
â Bit addressable data direction for each line
â Read/write of single line and 8-bit group
â Three 16-bit timer/counters
â Timers clocked by internal source
â Auto reload 8/16-bit timers
â Externally gated event counters
â Full-duplex serial port
â Synchronous mode, fixed baud rate
â 8-bit asynchronous mode, fixed baud rate
â 9-bit asynchronous mode, fixed baud rate
â 9-bit asynchronous mode, variable baud rate
â I2C bus controller - Master
â 7-bit and 10-bit addressing modes
â NORMAL, FAST, HIGH speeds
â Multi-master systems supported
â Clock arbitration and synchronization
â User defined timings on I2C lines
â Wide range of system clock frequencies
â Interrupt generation
â I2C bus controller - Slave
â NORMAL speed 100 kbs
â FAST speed 400 kbs
â HIGH speed 3400 kbs
â Wide range of system clock frequencies
â User defined data setup time on I2C lines
â Interrupt generation
â SPI â Master and Slave Serial Peripheral
Interface
â Supports speeds up ¼ of system clock
â Mode fault error
â Write collision error
â Four transfer formats supported
â System errors detection
â Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
â Interrupt generation
â Programmable Watchdog Timer
â 16-bit Compare/Capture Unit
â Events capturing
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD â Digital Core Design. All Rights Reserved.
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