DR80390XP Datasheet, PDF (5/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

BLOCK DIAGRAM
clk
reset
prgdatai(7:0)
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
xramdatai(7:0)
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
docddatai
docddatao
docdclk
Opcode
Decoder
Program
Memory
Interface
External
Memory
Interface
Internal Data
Memory
Interface
User SFR
Interface
DoCD™
Debug Unit
ALU
Control Unit
Interrupt
Controller
I/O Ports
int0
int1
int2
int3
int4
int5
int6
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
Power
Management
Unit
stop
pmm
Floating
Point Unit
Multiply
Divide Unit
t2
t2ex
Timer 2
capture0
capture1
capture2
capture3
rxd1o
rxd1i
txd1
msclhs
mscli
msclo
msdai
msdao
sscli
ssclo
ssdai
ssdao
Compare
Capture Unit
UART 1
Master
I2C Unit
Slave
I2C Unit
Timers 0 & 1
t0
gate0
t1
gate1
Watchdog
Timer
UART 0
SPI Unit
rxd0o
rxd0i
txd0
so
si
mo
mi
scko
scki
sckz
ss
sso(7:0)
PINS DESCRIPTION
PIN TYPE
DESCRIPTION
clk
reset
ramdatai[7:0]
sfrdatai[7:0]
prgdatai[7:0]
xramdatai[7:0]
int0
int1
int2
int3
int4
int5
int6
docddatai
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
t0
gate0
t1
gate1
t2
t2ex
capture0
capture1
capture2
capture3
rxd0i
rxd1i
mscli
msdai
sscli
ssdai
ss
si
mi
scki
ramdatao[7:0]
ramaddr[7:0]
ramoe
ramwe
sfrdatao[7:0]
sfraddr[7:0]
sfroe
sfrwe
prgaddr[23:0]
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
Global clock
Global synchronous reset
Data bus from Internal Data Memory
Data bus from user SFRs
Input data bus from Program Memory
Data bus from External Data Memory
External interrupt 0 line
External interrupt 1 line
External interrupt 2 line
External interrupt 3 line
External interrupt 4 line
External interrupt 5 line
External interrupt 6 line
DoCD™ data input
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Timer 0 clock line
Timer 0 clock line gate control
Timer 1 clock line
Timer 1 clock line gate control
Timer 2 clock line
Timer 2 control
Timer 2 capture 0 line
Timer 2 capture 1 line
Timer 2 capture 2 line
Timer 2 capture 3 line
Serial receiver input 0
Serial receiver input 1
Master I2C clock line input
Master I2C data input
Slave I2C clock line input
Slave I2C data input
SPI slave select
SPI slave input
SPI master input
SPI clock input
Data bus for Internal Data Memory
Internal Data Memory address bus
Internal Data Memory output enable
Internal Data Memory write enable
Data bus for user SFRs
User SFRs address bus
User SFRs output enable
User SFRs write enable
Program Memory address bus
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