DR80390XP Datasheet, PDF (3/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

● 16-bit Compare/Capture Unit
○ Events capturing
○ Pulses generation
○ Digital signals generation
○ Gated timers
○ Sophisticated comparator
○ Pulse width modulation
○ Pulse width measuring
● Fixed-Point arithmetic coprocessor
○ Multiplication - 16bit * 16bit
○ Division - 32bit / 16bit
○ Division - 16bit / 16bit
○ Left and right shifting - 1 to 31 bits
○ Normalization
● Floating-Point arithmetic coprocessor IEEE-
754 standard single precision
○ FADD, FSUB - addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
○ FUCOM - compare
○ FCHS - change sign
○ FABS - absolute value
● Floating-Point math coprocessor - IEEE-754
standard single precision real, word and
short integers
○ FADD, FSUB- addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
○ FUCOM- compare
○ FCHS - change sign
○ FABS - absolute value
○ FSIN, FCOS- sine, cosine
○ FTAN, FATAN- tangent, arcs tangent
CONFIGURATION
The following parameters of the DR80390XP
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
• Memory style
• Program Memory type
•
Program
states
Memory
wait-
• Program Memory writes
• Internal Data Memory type
•
External Data
wait-states
Memory
•
Second Data
(DPTR1)
Pointer
• Data Pointers decrement
• Data Pointers auto-switch
• Interrupts
• Timing access protection
• Power Management Mode
• Stop mode
• DoCD debug unit
- Harward
- von Neumann
- synchronous
- asynchronous
- used (0-7)
- unused
- used
- unused
- synchronous
- asynchronous
- used (0-7)
- unused
- used
- unused
- used
- unused
- used
- unused
-
subroutines
location
- used
- unused
- used
- unused
- used
- unused
- used
- unused
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
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