DR80390XP Datasheet, PDF (4/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor and
major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
SYMBOL
clk
reset
ramdatai(7:0)
sfrdatai(7:0)
prgdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
xramdatai(7:0)
int0
int1
int2
int3
int4
int5
int6
docddatai
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
docddatao
docdclk
stop
pmm
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
t0
gate0
t1
gate1
t2
t2ex
capture0
capture1
capture2
capture3
rxd0i
rxd1i
mscli
msdai
rxd0o
txd0
rxd1o
txd1
msclhs
msclo
msdao
sscli
ssdai
ssclo
ssdao
ss
sso(7:0)
si
so
mi
mo
scki
scko
sckz
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.