DR80390XP Datasheet, PDF (2/11 Pages) Digital Core Design – High Performance Configurable 8-bit Microcontroller ver 3.10

● User programmable External Data Memory
Wait States solution for wide range of
memories speed
● De-multiplexed Address/Data bus to allow
easy connection to memory
● Interface for additional Special Function
Registers
● Fully synthesizable, static synchronous de-
sign with positive edge clocking and no in-
ternal tri-states
● Scan test ready
● 1.3 GHz virtual clock frequency in a 0.35u
technological process
PERIPHERALS
● DoCD™ debug unit
○ Processor execution control
○ Run
○ Halt
○ Step into instruction
○ Skip instruction
○ Read-write all processor contents
○ Program Counter (PC)
○ Program Memory
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Hardware execution breakpoints
○ Program Memory
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Hardware breakpoints activated at a certain
○ Program address (PC)
○ Address by any write into memory
○ Address by any read from memory
○ Address by write into memory a required data
○ Address by read from memory a required data
○ Three wire communication interface
● Power Management Unit
○ Power management mode
○ Switchback feature
○ Stop mode
● Extended Interrupt Controller
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○ 2 priority levels
○ Up to 7 external interrupt sources
○ Up to 8 interrupt sources from peripherals
● Four 8-bit I/O Ports
○ Bit addressable data direction for each line
○ Read/write of single line and 8-bit group
● Three 16-bit timer/counters
○ Timers clocked by internal source
○ Auto reload 8/16-bit timers
○ Externally gated event counters
● Full-duplex serial port
○ Synchronous mode, fixed baud rate
○ 8-bit asynchronous mode, fixed baud rate
○ 9-bit asynchronous mode, fixed baud rate
○ 9-bit asynchronous mode, variable baud rate
● I2C bus controller - Master
○ 7-bit and 10-bit addressing modes
○ NORMAL, FAST, HIGH speeds
○ Multi-master systems supported
○ Clock arbitration and synchronization
○ User defined timings on I2C lines
○ Wide range of system clock frequencies
○ Interrupt generation
● I2C bus controller - Slave
○ NORMAL speed 100 kbs
○ FAST speed 400 kbs
○ HIGH speed 3400 kbs
○ Wide range of system clock frequencies
○ User defined data setup time on I2C lines
○ Interrupt generation
● SPI – Master and Slave Serial Peripheral
Interface
○ Supports speeds up ¼ of system clock
○ Mode fault error
○ Write collision error
○ Four transfer formats supported
○ System errors detection
○ Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○ Interrupt generation
● Programmable Watchdog Timer
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