DR80390CPU Datasheet, PDF (5/7 Pages) Digital Core Design – High Performance 8-bit Microcontroller ver 3.10

microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hard-
ware debugger provides debugging capability
of a whole SoC system. In contrast to other on-
chip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memo-
ries, all SFRs including user defined peripher-
als. Hardware breakpoints can be set and con-
trolled on program memory, internal and exter-
nal data memories, as well as on SFRs. Hard-
ware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. The DoCD™ system
includes three-wire interface and complete set
of tools to communicate and work with core in
real time debugging. It is built as scalable unit
and some features can be turned off to save
silicon and reduce power consumption. A spe-
cial care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when de-
bug option is no longer used.
PERFORMANCE
The following tables give a survey about the
Core area and performance in the ASICs De-
vices (all CPU features and peripherals have
been included):
Device
Optimization
0.25u typical
area
F_max
100 MHz
0.25u typical
speed
250 MHz
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR80390CPU clock periods} required to exe-
cute an identical function. More details are
available in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
7,20
6,00
6,00
7,20
7,20
6,00
6,00
7,20
10,67
9,60
7,20
7,64
9,75
7,20
7,43
9,04
7,58
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DR80390CPU
performance in terms of Dhrystone/sec and
VAX MIPS rating.
Device
Target
Clock
frequency
Dhry/sec
(VAX MIPS)
80C51
-
12 MHz
268 (0.153)
80C310
-
33 MHz 1550 (0.882)
DR80390CPU 0.25u
250 MHz 40125 (22.837)
Core performance in terms of Dhrystones
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
40125
268 ¹⁵⁵⁰
80C51 (12MHz)
DR80390CPU (90MHz)
80C310 (33MHz)
Area utilized by the each unit of DR80390CPU
core in vendor specific technologies is summa-
rized in table below.
Component
CPU*
Interrupt Controller
Power Management Unit
Area
[Gates]
5350
400
50
[FFs]
240
40
5
Total area
5800
285
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
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