DR80390CPU Datasheet, PDF (3/7 Pages) Digital Core Design – High Performance 8-bit Microcontroller ver 3.10

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LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
SYMBOL
clk
reset
ramdatai(7:0)
sfrdatai(7:0)
prgdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
xramdatai(7:0)
int0
int1
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
docddatai
docddatao
docdclk
stop
pmm
BLOCK DIAGRAM
clk
reset
prgdatai(7:0)
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
xramdatai(7:0)
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
Opcode
Decoder
Program
Memory
Interface
External
Memory
Interface
Internal Data
Memory
Interface
User SFR
Interface
ALU
Control Unit
Interrupt
Controller
Power
Management
Unit
DoCD™
Debug Unit
int0
int1
stop
pmm
docddatai
docddatao
docdclk
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