DR80390CPU Datasheet, PDF (4/7 Pages) Digital Core Design – High Performance 8-bit Microcontroller ver 3.10

PINS DESCRIPTION
PIN TYPE
DESCRIPTION
clk
reset
ramdatai[7:0]
sfrdatai[7:0]
prgdatai[7:0]
xramdatai[7:0]
int0
int1
docddatai
ramdatao[7:0]
ramaddr[7:0]
ramoe
ramwe
sfrdatao[7:0]
sfraddr[7:0]
sfroe
sfrwe
prgaddr[23:0]
prgdatao[7:0]
prgdataz
prgrd
prgwr
xramdatao[7:0]
xramdataz
xramaddr[23:0]
xramrd
xramwr
docddatao
docdclk
pmm
stop
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
Global clock
Global synchronous reset
Data bus from Internal Data Memory
Data bus from user SFRs
Input data bus from Program Memory
Data bus from External Data Memory
External interrupt 0 line
External interrupt 1 line
DoCD™ data input
Data bus for Internal Data Memory
Internal Data Memory address bus
Internal Data Memory output enable
Internal Data Memory write enable
Data bus for user SFRs
User SFRs address bus
User SFRs output enable
User SFRs write enable
Program Memory address bus
Output data bus for Program Memory
PRGDATA tri-state buffers control line
Program Memory read
Program Memory write
Data bus for External Data Memory
XDATA tri-state buffers control line
External Data Memory address bus
External Data Memory read
External Data Memory write
DoCD™ data output
DoCD™ clock line
Power management mode indicator
Stop mode indicator
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module. Program fetch cycle length
can be programmed by user. This feature is
called Program Memory Wait States, and al-
lows core to work with different speed program
memories.
External Memory Interface – Contains mem-
ory access related registers such as Data
Pointer High (DPH0), Data Pointer Low
(DPL0), Data Page Pointer (DPP0), MOVX
@Ri address register (MXAX) and STRETCH
registers. It performs the memory addressing
and data transfers. Allows applications soft-
ware to access up to 16 MB of external data
memory. The DPP0 register is used for seg-
ments swapping. STRETCH register allows
flexible timing management while accessing
different speed system devices by program-
ming XRAMWR and XRAMRD pulse width
between 1 – 8 clock periods.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Man-
agement Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
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