DR80390CPU Datasheet, PDF (2/7 Pages) Digital Core Design – High Performance 8-bit Microcontroller ver 3.10

● Fully synthesizable, static synchronous de-
sign with positive edge clocking and no in-
ternal tri-states
● Scan test ready
● 1.3 GHz virtual clock frequency in a 0.35u
technological process
PERIPHERALS
● DoCD™ debug unit
○ Processor execution control
○ Run
○ Halt
○ Step into instruction
○ Skip instruction
○ Read-write all processor contents
○ Program Counter (PC)
○ Program Memory
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Hardware execution breakpoints
○ Program Memory
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Hardware breakpoints activated at a certain
○ Program address (PC)
○ Address by any write into memory
○ Address by any read from memory
○ Address by write into memory a required data
○ Address by read from memory a required data
○ Three wire communication interface
● Power Management Unit
○ Power management mode
○ Switchback feature
○ Stop mode
● Interrupt Controller
○ 2 priority levels
○ 2 external interrupt sources
CONFIGURATION
The following parameters of the DR80390CPU
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
• Memory style
- Harward
- von Neumann
• Program Memory type
- synchronous
- asynchronous
•
Program
states
Memory
wait-
- used (0-7)
- unused
• Program Memory writes
- used
- unused
• Internal Data Memory type
- synchronous
- asynchronous
•
External Data
wait-states
Memory
- used (0-7)
- unused
• Interrupts
-
subroutines
location
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD debug unit
- used
- unused
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor and
major versions changes
● Delivery the documentation updates
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.